In Volume EDL-2, No. 10, October 1981 of IEEE Electron Device Letters at page 250, J. P. Colinge and E. Demoulin presented a paper entitled "A High Density CMOS Inverter with Stacked Transistors". This paper describes a complete CMOS inverter, whose P-channel transistors made from laser annealed polycrystalline silicon and is superimposed upon the N-channel transistor made in a bulk silicon substrate. The single gate is common to both transistors. The process is NMOS compatible and polysilicon transistors with channel lengths down to four micrometers have been made. However, the prior art does not teach metal gate PMOS, polygate NMOS wherein both are self-aligning. Neither does the prior art teach a two-layer device with one type device built on bulk silicon and a single type built on a recrystallized polysilicon layer where only a single polylayer is employed. The same is true for CMOS devices and enhancement-depletion devices utilizing either NMOS or PMOS technology. Since isolation wells are not used to isolate the NMOS from PMOS, all common PNPN paths are eliminated so that the CMOS bulk devices are latch-up free--all with an increased density advantage over existing techniques because of the elimination of space taken up by isolation wells.